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January 1998
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ICL7112
12-Bit, High-Speed, CMOS P-Compatible A/D Converter
Description
The ICL7112 is a monolithic 12-bit resolution, fast successive approximation A/D converter. It uses thin film resistors and CMOS circuitry combined with an on-chip PROM calibration table to achieve 12-bit linearity without laser trimming. Special design techniques used in the DAC and comparator result in high speed operation, while the fully static silicon-gate CMOS circuitry keeps the power dissipation very low. Microprocessor bus interfacing is eased by the use of standard memory WRite and ReaD cycle timing and control signals, combined with Chip Select and Address pins. The digital output pins are byte-organized and three-state gated for bus interface to 8-bit and 16-bit systems. The lCL7112 provides separate Analog and Digital grounds for increased system accuracy. Operating with 5V supplies, the lCL7112 accepts 0V to +10V input with a -10V reference or 0V to -10V input with a +10V reference.
Features
* 12-Bit Resolution and Accuracy * No Missing Codes * Microprocessor Compatible Byte-Organized Buffered Outputs * Auto-Zeroed Comparator for Low Offset Voltage * Low Linearity and Gain Errors * Low Power Consumption (60mW) * No Gain or Offset Adjustment Necessary * Provides 3% Usable Overrange * Fast Conversion (40s)
Ordering Information
PART NO. ICL7112JCDL ICL7112KCDL ICL7112LCDL ICL7112JIDL ICL7112KIDL ICL7112LIDL ICL7112JMDL ICL7112KMDL ICL7112LMDL NOTE: Over operating temperature range. TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 -25 to 85 -25 to 85 -25 to 85 -55 to 125 -55 to 125 -55 to 125 PACKAGE 40 Ld CERDIP 40 Ld CERDIP 40 Ld CERDIP 40 Ld CERDIP 40 Ld CERDIP 40 Ld CERDIP 40 Ld CERDIP 40 Ld CERDIP 40 Ld CERDIP RESOLUTION WITH NO MISSION CODES 11-Bit 12-Bit 12-Bit (Note) 11-Bit 12-Bit 12-Bit (Note) 11-Bit 12-Bit 12-Bit (Note)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 6-1
File Number
3639.1
ICL7112 Pinout
ICL7112 TOP VIEW
NC AGNDf CS RD A0 BUS DGND (MSB) D 11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 (LSB) D0 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 NC 39 AGNDs 38 VREF 37 VIN 36 COMP 35 V 34 CAZ 33 WR 32 TEST
ICL7112
31 OSC2 30 OSC1 29 TEST 28 PROG 27 V + 26 OVR 25 EOC 24 NC 23 NC 22 NC 21 NC
Functional Block Diagram
VREF VIN RIN AGND DAC R-1.85R CAZ OSC1 OSC2
COMP
+ -
Y+ DGND V-
SAR CONTROL LOGIC
WR EOC
PROM
LATCH
LATCH
THREE-STATE OUTPUTS
OVR D11 (MSB) D0 (LSB)
ADDER ACCCUM RD CS A0 BUS
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ICL7112
Absolute Maximum Ratings TA = 25oC
Supply Voltage (V + to DGND) . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Supply Voltage (V - to DGND). . . . . . . . . . . . . . . . . . . +0.3V to -6.5V VREF , VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1V to -1V VREF , VIN , AGND Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Digital I/O Pin Voltages. . . . . . . . . . . . . . . . . . . . . -0.3V to V+ +0.3V PROG to DGND Voltage . . . . . . . . . . . . . . . . . . . . V - to (V+ +0.3V)
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . ___ ___ Maximum Power Dissipation (Note 2). . . . . . . . . . . . . . . . . . 500mW Derate above 70oC at 10mW/oC Maximum Junction Temperature (Ceramic Package) . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
Operating Conditions
ICL7112XCXX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70 ICL7112XIXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 to 70 ICL7112XMXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 125
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. All voltages with respect to DGND, unless otherwise noted. 3. Assumes all leads soldered or welded to printed circuit board.
Electrical Specifications
PARAMETER ACCURACY Resolution RES SYMBOL
Test Conditions: V+ = +5V, V- = -5V, VREF = -10V, TA = 25oC, fCLK = 500kHz, Unless Otherwise Noted TEST CONDITIONS J MIN TYP MAX 12 MIN K TYP MAX MIN L TYP MAX UNITS Bits 12 11 0.012 0.020 0.08 0.10 0.08 0.11 0.08 0.12 1 1.5 10.3 9 12 12 Bits
Resolution with No RES Missing Codes (NMC) Integral Linearity Error Unadjusted Full Scale Error ILE FSE
Notes 4, 5, 6 Notes 4, 5 Adjustable to Zero C
RM TMIN -TMAX RM TMIN -TMAX RM TMIN TMAX RM TMIN -TMAX TMIN -TMAX RM
11 10 -
-
0.024 0.030 0.10 0.12 0.10 0.13 0.10 0.14 1 1.5 10.3 9 -
0.012 %FSR 0.020 0.08 0.10 0.08 0.11 0.08 0.12 1 1.5 10.3 9 V k ppm/oC
I M Zero Error ANALOG INPUT Analog Input Range Input Resistance Temperature Coefficient of RIN Analog Reference Reference Resistance Power Supply Rejection Ration LOGIC INPUT Low State Input Voltage VIL VIN RIN TC (R IN) Notes 5, 8 ZE Notes 4, 5
-
-
-
-
-
-
%FSR
RM TMIN -TMAX
0 4 TMIN -TMAX -
-300
0 4 -
-300
0 4 -
-300
REFERENCE INPUT V REF RREF -10.0 5 -10.0 5 -10.0 5 V k
POWER SUPPLY SENSITIVITY PSRR RM V +, V - = 4.5 -5.5V TMIN -TMAX TMIN -TMAX 0.5 1 2 0.8 0.5 1 2 0.8 0.5 1 2 0.8 LSB
-
-
-
-
-
-
V
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ICL7112
Electrical Specifications
PARAMETER High State Input Voltage Logic Input Current Logic Input Capacitance LOGIC OUTPUT Low State Output Voltage High State Output Voltage VOL VOH IOUT = 1.6mA TMIN -TMAX IOUT = -200A TMIN -TMAX 0 < VOUT < V+ Three-State 2.8 1 15 0.4 2.8 1 15 0.4 2.8 1 15 0.4 V V A pF SYMBOL VIH ILIH CIN 0 < VIN < V+ Test Conditions: V+ = +5V, V- = -5V, VREF = -10V, TA = 25oC, fCLK = 500kHz, Unless Otherwise Noted TEST CONDITIONS TMIN -TMAX J MIN 2.4 TYP 1 15 MAX 10 MIN 2.4 K TYP 1 15 MAX 10 MIN 2.4 L TYP 1 15 MAX 10 UNITS V A pF
Three-State Output IOX Current Logic Output Capacitance Supply Voltage Range Supply Current, I+, INOTES: COUT
POWER REQUIREMENTS VSUPPLY Functional Operation Only ISUPPLY RM TMIN -TMAX 4.5 2 6.0 4 6 4.5 2 6.0 4 6 4.5 2 6.0 4 6 V mA
4. Full scale range (FSR) is 10V (reference adjusted). 5. Assume all leads are soldered or welded to printed circuit board. 6. "J" and "K" versions not production tested. Guaranteed by Integral Linearity Test. 7. Typical values are not tested, for reference only. 8. Not production tested. Guaranteed by design.
AC Electrical Specifications Test Conditions V+ = +5V, V- = -5V, TA = 25oC, fCLK = 500kHz, unless otherwise noted. Data
derived from extensive characterization testing. Parameters are not production tested PARAMETER READ CYCLE TIMING Propagation Delay CS to Date Propagation Delay A0 to Data Propagation Delay RD to Data Propagation Delay Data to Three-State Propagation Delay EOC High to Data WRITE CYCLE TIMING WR Low Time Propagation Delay WR Low to EOC Low EOC High Time Conversion Time Clock Frequency Range NOTE: 9. All typical values have been characterized, but are not tested. t wr t we t eo t conv f CLK Functional Operation Only Wait Mode Free Run Mode 150 1 0.5 500 2 1.5 20 kHz 1/fCLK ns t cd t ad t rd t rx t ed RD Low, A0 Valid CS Low, RD Low CS Low, A0 Valid 200 200 200 150 200 ns SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
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ICL7112 Pin Descriptions
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 EOC OVR V+ PROG TEST OSC1 OSC2 TEST WR CAZ VCOMP VIN VREF AGNDs AGNDf CS RD A0 BUS DGND D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME No connection. FORCE input for analog ground. Chip Select enables reading and writing (active low). ReaD (active low). Byte select (low = D0 -D7, high = D 8 -D 11, OVR). Bus select (low = outputs enabled by A0, high = all outputs enabled together). Digital GrouND return. Bit 11 (most significant bit). Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (least significant bit). No connection. No connection. No connection. No connection. No connection. End of conversion flag (low = busy, high = conversion complete). OVerRange flag (valid at end of conversion when output code exceeds full-scale; three-state output enabled with high byte). Positive power supply input. Used for programming only. Must tie to V+ for normal operation. Used for programming only. Must tie to V+ for normal operation. Oscillator inverter input. Oscillator inverter output. Must tie to V+ for normal operation. WRite pulse input (low starts new conversion). Auto-zero capacitor connection (Note). Negative power supply input. Used in test, tie to V -. SENSE line for input voltage. SENSE line for reference input. SENSE line for analog ground. No connection Output Data Bits (High =True) Low Byte High Byte DESCRIPTION
NOTE: The voltage of CAZ is driven; NEVER connect directly to ground.
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ICL7112 Timing Diagrams
CS A0 tCD
VALID tAD
RD tRD D0 - D13 EOC = DON'T CARE tED tRX VALID
FIGURE 1. READ CYCLE TIMING
CS tWR WR tWE EOC tEO = DON'T CARE tCONV
FIGURE 2. WRITE CYCLE TIMING TABLE 2: CS WR RD A0 0 1 0 0 0 x 0 x x x x x x x 0 0 0 1 x x 0 1 x x BUS x x 0 0 1 x I/O CONTROL FUNCTION Initiates a conversion. Disables all chip commands. Low byte is enabled. High byte is enabled. Low and High bytes enabled together. Disables outputs (high-impedance). TRANSFER FUNCTION EXPECTED OUTPUT CODE OVR 0 0 0 0 0 0 0 1 1 1 MSB 0 0 0 0 1 1 1 0 0 0 0000000000 0000000000 0000111101 1111111111 0000000000 1111111111 1111111111 0000000000 0000000000 0000111101 LSB 0 1 1 1 0 0 1 0 1 1
a standard SAR-type converter. The Functional Block Diagram shows the functional diagram of the ICL7112 12-bit A/D converter. The additional circuitry incorporated into the ICL7112 is used to perform error correction and to maintain the operating speed in the 40s range. The internal DAC of the ICL7112 is designed around a radix of 1.85, rather than the traditional 2.00. This radix gives each bit of the DAC a weight of approximately 54% of the previous bit. The result is a usable range that extends to 3% beyond the full-scale input of the A/D. The actual value of each bit is measured and stored in the on-chip PROM. The absolute value of each bit weight then becomes relatively unimportant because of the error correction action of the ICL7112. The output of the high-speed auto-zeroed comparator is fed to the data input of a successive approximation register (SAR). This register is uniquely designed for the ICL7112 in that it tests bit pairs instead of individual bits in the manner of a standard SAR. At the beginning of the conversion cycle, the SAR turns on the MSB (D11) and the MSB 4-bit (D7). The sequence continues for each bit pair, BX and Bx-4 , until only the four LSBs remain. The sequence concludes by testing the four LSBs individually. The SAR output is fed to the DAC register and to the preprogrammed PROM where it acts as PROM address. PROM data is fed to a full-adder/accumulator where the decoded results from each successive phase of the conversion are summed with the previous results. After 20 clock cycles, the accumulator contains the final binary data which is latched and sent to the three-state output buffers. The accuracy of the A/D converter depends primarily upon the accuracy of the data that has been programmed into the PROM during
TABLE 3: INPUT VOLTAGE VREF = -10.0V 0 +0.00244 +0.30029 +4.99756 +5.00000 +9.99512 +9.99756 +10.00000 +10.00244 +10.29000
Detailed Description
The ICL7112 is basically a successive approximation A/D converter with an internal structure much more complex than
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ICL7112
the final test portion of the manufacturing process. The error correcting algorithm built into the ICL7112 reduces the initial accuracy requirements of the DAC. The overlap in the testing of bit pairs reduces the accuracy requirements on the comparator which has been optimized for speed. Since the comparator is auto-zeroed, no external adjustment is required to get ZERO code for ZERO input voltage. Twenty clock cycles are required for the complete 12-bit conversion. The auto-zero circuitry associated with the comparator is employed during the last three clock cycles of the conversion to cancel the effect of offset voltage. Also during this time, the SAR and accumulator are reset in preparation for the start of the next conversion. The overflow output of the full-adder is also the OVer Range (OVR) output of the ICL7112. Unlike standard SAR type A/D converters, the ICL7112 has the capability of providing valid usable data for inputs that exceed the fullscale range by as much as 3%. voltage and with the digital output. Even the auto-zero loop of the ICL7112 cannot remove this error. Figure 4 shows a much better arrangement. The ground and reference currents do not flow through the input common lead, eliminating any error voltages. Note that the supply currents and any other analog system currents must also be returned carefully to analog ground. The clamp diodes will protect the ICL7112 against signals which could result from separate analog and digital grounds. The absolute maximum voltage rating between AGND and DGND is 1.0V. The two inverse-parallel diodes clamp this voltage to less than 0.7V.
Input Warning
As with any CMOS integrated circuit, no input voltages should be applied to the lCL7112 until the 5V power supplies have stabilized.
Interfacing To Digital Systems
The_ICL7112 provides three-state data output buffers, CS, RD, WR, and bus select inputs (A0 and BUS) for interfacing to a wide variety of microcomputers and digital systems. The I/O Control Truth Table shows the functions of the digital control lines. The BUS select and A0 lines are provided to enable the output data onto either 8-bit or 16-bit data buses. A conversion is initiated by a WR pulse (pin 33) when CS (pin 3) is low. Data is enabled on the bus when the chip is selected and RD (pin 4) is low. Figure 5 illustrates a typical interface to an 8-bit microcomputer. The "Start and Wait" operation requires the fewest external components and is initiated by a low level on the WR input to the ICL7112 after the I/O or memory mapped address decoder has brought the CS input low. After executing a delay or utility routine for a period of time greater than the conversion time of the ICL7112, the processor issues two consecutive bus addresses to read output data into two bytes of memory. A low level on A0 enables the LSBs, and a high level enables the MSBs.
Optimizing System Performance
When using A/D converters with 12 or more bits of resolution, special attention must be paid to grounding and the elimination of potential ground loops. A ground loop can be formed by allowing the return current from the lCL7112's DAC to flow through traces that are common to other analog circuitry. If care is not taken, this current can generate small unwanted voltages that add to or detract from the reference or input voltages of the A/D converter. Figure 3 and Figure 4 show two different grounding techniques. Although the difference between the two circuits may not be readily apparent, the circuit of Figure 3 is very likely to have significant ground loop errors which the circuit of Figure 4 avoids. In Figure 3, the supply currents for analog ground, digital ground, and the reference voltage all flow through a lead, common to the input. This will generate a DC offset voltage due to the currents flowing in the resistance of the common lead. This offset voltage will vary with the input
VIN + SOURCE VREF SOURCE +
VIN ICL7112 VREF AGND DGND
FIGURE 3. IMPROPER GROUNDING TECHNIQUE WILL CAUSE GROUND LOOP ERRORS
6-7
ICL7112
VIN + SOURCE VREF SOURCE + AGND VIN ICL7112 VREF
DGND
FIGURE 4. RECOMMENDED GROUNDING TECHNIQUE TO ELIMINATE GROUND LOOP ERRORS
ADDRESS BUS A0
A0 ICL7112 CS RD WR BUS OVR D0 - D7 D8 - D11
ADDRESS DECODE
A0 - AN
CS RD WR P
OVR D0 - D7
DATA BUS
WR
CS
A0
RD START CONVERSION WAIT READ LOW BYTE READ HIGH BYTE
FIGURE 5. "START AND WAIT" OPERATION
By adding a three-state buffer and two control gates, the End-of-Conversion (EOC) output can be used to control a "Start and Poll" interface (Figure 6). In this mode, the A0 and CS lines connect the EOC output to the data bus along with the most significant byte of data. After pulsing the WR line to initiate a conversion, the microprocessor continually reads the most significant byte until it detects a high level on the EOC bit. The "Start and Poll" interface increases data throughput compared with the "Start and Wait" method by eliminating delays between the conversion termination and
the microprocessor read operation. Other interface configurations can be used to increase data throughput without monopolizing the microprocessor during waiting or polling operations by using the EOC line as an interrupt generator as shown in Figure 7. After the conversion cycle is initiated, the microprocessor can continue to execute routines that are independent of the A/D converter until the converter's output register actually holds valid data. For fastest data throughput, the ICL7112 can be connected directly to the data bus but controlled by way of a Direct
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ICL7112
Memory Access (DMA) controller as shown in Figure 8.
Applications
Figure 9 shows a typical application of the ICL7112 12- bit A/D converter. A bipolar input voltage range of +10V to -10V is the result of using the current through R2 to force a 1/2 scale offset on the input amplifier (A1). The output of A1 swings from 0V to -1 0V. The overall gain of the A/D is varied by adjusting the 100 trim resistor, R5 . Since the ICL7112 is automatically zeroed every conversion, the system gain and offset stability will be superb as long as a reference with a tempco of 1ppm/oC and stable external resistors are used. If is important to note that since the 7112's DAC current flows in A1 , the amplifier should be a wideband (GBW > 20MHz) type to minimize errors. The clock for the ICL7112 is taken from whatever system clock is available and divided down to the level for a conversion time of 40s. Output data is controlled by the BUS and A0 inputs. Here they are set for 8-bit bus operation with BUS grounded and A0 under the control of the address decode section of the external system. Because the ICL7112's internal accumulator generates accurate output data for input signals as much as 3% greater than full-scale, and because the converter's OVR output flags overrange inputs, a simple microprocessor routine can be employed to precisely measure and correct for system gain and offset errors. Figure 10 shows a typical data acquisition system that uses a 10V reference, input signal multiplexer, and input signal Track/Hold amplifier. Two of the multiplexer's input channels are dedicated to sampling the system analog ground and reference voltage. Here, as in Figure 9, bipolar operation is accommodated by an offset resistor between the reference voltage and the summing junction of A1 . A flip-flop in IC3 sets 1C2's Track/Hold input after the microprocessor has initiated a WR command, and resets when EOC goes high at the end of the conversion. The first step in the system calibration routine is to select the multiplexer channel that is connected to system analog ground and initiate a conversion cycle for the ICL7112. The results represent the system offset error which comes from the sum of the offsets from IC 1 , IC 2 , and A1 . Next the channel connected to the reference voltage is selected and measured. These results, minus the system offset error, represent the system full-scale range. A gain error correction factor can be derived from this data. Since the lCL7112 provides valid data for inputs that exceed full-scale by as much as 3%, the OVR output can be thought of as a valid 13th data bit. Whenever the OVR bit is high, however, the total 12-bit result should be checked to ensure that it falls within 100% and 103% of full-scale. Data beyond 103% of fullscale should be discarded.
Clock Considerations
The ICL7112 provides an internal inverter which is brought out to pins OSC1 and OSC2, for crystal or ceramic resonator oscillator operation. The clock frequency is calculated from:
20 fCLK = ----------------t C ONV
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ICL7112
() ADDRESS BUS A0
A0 ICL7112 WR CS RD
ADDRESS DECODE
A0 - AN
WR RD P
CS
EOC BUS D0 - D7 D8 - D 11 OVR 1/4 74125 D0 - D7
DATA BUS (B) END OF CONVERSION
WR CS EOC
A0
RD START CONVERSION POLL READ HIGH BYTE READ HIGH BYTE READ LOW BYTE
FIGURE 6. START AND POLL" OPERATION
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ICL7112
ADDRESS BUS A0
A0
ADDRESS DECODE
A0 - AN
CS RD WR ICL7112 RD WR P
EOC BUS OVR D0 - D 7 D8 - D11
INT
D0 - D7
DATA BUS
INTERRUPT WR
CS
EOC
A0
RD START CONVERSION READ LOW BYTE READ HIGH BYTE
FIGURE 7. USING EOC AS AN INTERRUPT
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ICL7112
ADDRESS BUS A0
A0 ICL7112
WR
A0 - A11
EOC RD CS BUS OVR D0 - D7 D8 - D11
DRQN DACKN
CS
DMA CONTROLLER
D0 - D7
DATA BUS
EOC
DACKN
A0 READ LOW BYTE END OF CONVERSION READ HIGH BYTE START CONVERSION
FIGURE 8. DATA TO MEMORY VIA DMA CONTROLLER
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ICL7112
+5V
28 R4 10V REFERENCE R1 100k HI INPUT VOLTAGE +10V TO -10V PROG TEST
32 TEST
29
27 500KHz V+ OSC 30 DIVIDER 25 26 SYSTEM CLOCK
R5 100K R2 100k A2 34 0.22F R3 50k 36 37
VREF VIN
EOC DATA
+
CAZ ICL7112 OUT
HIGH BYTE 13 14 LOW BYTE 21
8-BIT DATA BUS
LO A2 39
AGND WR AGND 2 RD CS A0 DIODES 1N914 COMP 36 V+ 35
33 4 3 5 ADDRESS DECODE
+
DGND 7
BUS 6
PINS 1, 20, 21, 22, 23, 24, 40 NO CONNECTIONS
-5V
DIGITAL GROUND
FIGURE 9. TYPICAL APPLICATION WITH BIPOLAR INPUT RANGE, FORCED GROUND, AND 10V ULTRA STABLE REFERENCE
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ADDRESS BUS REFERENCE 10V VCC ADDRESS DECODE
ADDRESS DECODE IS
VREF VS
A0
BUS CS RD WR RD WR
A0 - AN
ANALOG INPUTS
IC1 IH5108 OUT IR A0 - A2
ICL7112 IC 2 LF398 EOC 10k + VR OVR 1/2 74125
P
D8 - D13 D0 - D7
D0 - D 7
Q DATA LATCH D IC3 1/2 4013
R
S
DATA BUS
FIGURE 10. MULTI-CHANNEL DATA ACQUISITION SYSTEM WITH ZERO AND REFERENCE LINES BROUGHT TO MULTIPLEXER FOR SYSTEM GAIN AND OFFSET ERROR CORRECTION
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